Power and performance optimization techniques for multi-core processors

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Chip multiprocessors (CMPs) are becoming mainstream, making parallel programming necessary to utilize computational power provided by many cores. However, the grand challenge is to make parallelism pervasive and make it accessible for average programmers. The main difficulty of parallel programming comes from synchronization; concurrent accesses to a memory location should be coordinated to ensure that they do not interfere. This research proposal aims at improving power- and performance-efficiency of synchronization in chip multiprocessors.