Power and performance optimization techniques for multi-core processors

芯片多处理器（CMP）正在成为主流，使得并行编程必须利用许多核心提供的计算能力。然而，最大的挑战是使并行性无处不在，并使其为普通程序员所用。并行编程的主要困难来自同步;对内存位置的并发访问应该协调，以确保它们不会相互干扰。该研究提案旨在提高芯片多处理器同步的功耗和性能效率。

Chip multiprocessors (CMPs) are becoming mainstream, making parallel programming necessary to utilize computational power provided by many cores. However, the grand challenge is to make parallelism pervasive and make it accessible for average programmers. The main difficulty of parallel programming comes from synchronization; concurrent accesses to a memory location should be coordinated to ensure that they do not interfere. This research proposal aims at improving power- and performance-efficiency of synchronization in chip multiprocessors.