ANR_Single electron device integration on CMOS technology (Joint research project with Agence National de Recherche, France)

ANR_CMOS技术上的单电子器件集成（与法国国家研究机构的联合研究项目）

• 批准号: 380978-2009
• 负责人: Drouin, Dominique
• 金额: $ 14.55万
• 依托单位: Université de Sherbrooke
• 依托单位国家: 加拿大
• 项目类别: Strategic Projects - Group
• 财政年份: 2009
• 资助国家: 加拿大
• 起止时间: 2009-01-01 至 2010-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=438566
• 关键词: ANR_Single; electron; device; integration; CMOS

Since the creation of the integrated circuit, more than 4 decades ago, a tenfold increase in computing performance has been achieved every 5 years. The most significant impact of this trend is the continuing decrease of cost-per-chip which has led to significant improvement in economic productivity and overall quality of life though the proliferation of computers, communication and electronics in general. This outstanding improvement is essentially due to the scaling down of the CMOS technology (Complementary Metal Oxide Semiconductor). The aim of this project is not to replace CMOS circuits for general purpose Boolean logic but rather to develop enhanced CMOS technology by adding new functionalities through heterogeneous integration of new nanodevices. The objective of this project consists in stacking Single Electron Devices (SED) (transistors or memories) on existing CMOS technology and providing the tools to make use of such hybrid SED-CMOS technology. The advantages of such an approach are numerous and address major concerns of the industry: larger integration density (3-D vs 2-D), reduced interconnect lengths (to overcome SED fan-out issues), non invasive technology (CMOS fabrication process is not disturbed). This project is presented by a consortium of researchers from the Center of Excellence in Information Engineering at Universite de Sherbrooke, the Laboratory for Micro and Nanofabrication at INRS- Energy, Materials and Telecommunications, Lyon Institute of Nanotechnology at INSA-Lyon in France,

自40多年前集成电路诞生以来，计算性能每5年就能提高10倍。这一趋势的最重要影响是每芯片成本的持续下降，这导致了经济生产力和整体生活质量的显着改善，尽管计算机，通信和电子产品的普及。这种显著的改进主要是由于CMOS技术（互补金属氧化物半导体）的缩小。该项目的目的不是取代通用布尔逻辑的CMOS电路，而是通过新纳米器件的异质集成增加新功能来开发增强的CMOS技术。该项目的目标是在现有CMOS技术上堆叠单电子器件（SED）（晶体管或存储器），并提供使用这种混合SED-CMOS技术的工具。这种方法的优点很多，解决了业界的主要问题：更大的集成密度（3-D vs 2-D），减少互连长度（以克服SED扇出问题），非侵入性技术（CMOS制造工艺不受干扰）。该项目由来自舍布鲁克大学信息工程卓越中心，INRS-能源，材料和电信实验室，法国INSA-里昂纳米技术研究所的里昂纳米技术研究所的研究人员组成的联盟提出，