A study on decimal floating-point arithmetic unit through fused multiply-add architecture

自从1985年电气和电子工程师协会(IEEE)754二进制浮点标准被采用以来，每个微处理器和许多编程语言都指定了符合IEEE 754标准的浮点。最近，在金融分析、税务计算、电话计费、货币兑换、基于互联网的应用和电子商务等许多商业应用中，对十进制浮点(DFP)算术运算的需求不断增加。因此，用于DFP算术运算的规范最近被添加到IEEE浮点算术标准(IEEE754-2008)。由于许多十进制小数(例如，0.1)不能用二进制精确表示，因此以十进制格式存储数据并使用十进制算术处理数据是可取的。即使DFP算术软件消除了转换错误，DFP软件通常也比硬件中实现的等效二进制浮点(BFP)慢100到1000倍。因此，开发高效的DFP运算器硬件实现是非常重要的。

Since the Institute of Electrical and Electronics Engineers (IEEE) 754 binary floating-point standard was adopted in 1985, every microprocessor and many programming languages have specified IEEE 754 compliant floating-point. Recently, there has been increased demand for decimal floating-point (DFP) arithmetic operations in many commercial applications, including financial analyses, tax calculations, phone billing, currency conversion, Internet-based applications, and e-commerce. Consequently, specifications for DFP arithmetic operations have recently been added to the IEEE Standard for Floating-Point Arithmetic (IEEE754-2008). Because many decimal fractional numbers (e.g., 0.1) cannot be exactly represented in binary, storing data in a decimal format and processing data using decimal arithmetic is desirable. Even if DFP arithmetic software eliminates conversion errors, DFP software is typically 100 to 1,000 times slower than equivalent binary floating-point (BFP) implemented in hardware. Therefore, it is very important to develop efficient hardware implementations of DFP arithmetic units.