A study on decimal floating-point arithmetic unit through fused multiply-add architecture

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Since the Institute of Electrical and Electronics Engineers (IEEE) 754 binary floating-point standard was adopted in 1985, every microprocessor and many programming languages have specified IEEE 754 compliant floating-point. Recently, there has been increased demand for decimal floating-point (DFP) arithmetic operations in many commercial applications, including financial analyses, tax calculations, phone billing, currency conversion, Internet-based applications, and e-commerce. Consequently, specifications for DFP arithmetic operations have recently been added to the IEEE Standard for Floating-Point Arithmetic (IEEE754-2008). Because many decimal fractional numbers (e.g., 0.1) cannot be exactly represented in binary, storing data in a decimal format and processing data using decimal arithmetic is desirable. Even if DFP arithmetic software eliminates conversion errors, DFP software is typically 100 to 1,000 times slower than equivalent binary floating-point (BFP) implemented in hardware. Therefore, it is very important to develop efficient hardware implementations of DFP arithmetic units.