Efficient hardware implementations of decimal floating-point arithmetic unit

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Recently, there are significant demands for decimal arithmetic operations for many commercial applications, including financial analysis, tax calculation, phone billing, currency conversion, Internet based applications, and e-commerce. Consequently, specifications for decimal arithmetic operations have recently been added to the unapproved draft (as of Oct. 2006) of the Institute of Electrical and Electronics Engineers (IEEE) 754 Standard for Floating-Point Arithmetic. Binary floating-point arithmetic in hardware can handle decimal arithmetic-intensive applications, but decimal data can be more accurately represented by a decimal arithmetic unit. Since many decimal numbers cannot be exactly represented in binary, it is desirable to store data in a decimal format and process data using decimal arithmetic software. Even if decimal floating-point arithmetic software eliminates conversion errors, it is known that decimal floating-point software is typically 100 to 1,000 times slower than binary floating-point implemented in hardware. Therefore, there is need for hardware implementations of decimal floating-point arithmetic. Efficient hardware implementations of decimal floating-point arithmetic unit will be studied in this proposed research. The result of this research will improve the performance and the accuracy of many commercial applications significantly.Floating-point hardware offers a wide dynamic range and high computation precision, yet occupies large fractions of total chip area and power consumption. Therefore its usage, especially in low-power applications, is limited. Many embedded microprocessors do not include a floating-point unit due to its unacceptable hardware cost. This proposed research will explore a way of reducing decimal floating-point hardware cost and power consumption by minimizing the bit-width representation of decimal floating-point data. The result of decimal floating-point bit width-reduction can deliver a significant hardware cost and power saving through the use of a minimized decimal bit-width floating-point unit.