High performance and energy efficient deep learning processor design

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As sensors spread everywhere, the internet of things is going to trigger a massive inflow of big data. Incredible growth in the number of sensors will contribute to even larger amounts of data in the coming years. Software exploits an artificial intelligence technique known as deep learning, which uses simulated neurons and synapses to process data. Deep learning has produced dramatic advances in processing big data like images and audio in recent years. Deep learning systems are promising in various areas including biomedical/health informatics, self-driving cars, computer vision, natural language processing, and big data analysis applications. In many of these applications, deep learning systems can achieve near or even above human performance.***Although deep learning systems are powerful, the cost to realize the algorithms is very expensive. Deep learning algorithms are computation and memory intensive. Training a data set for a deep learning solution requires massive data. To perform a task to solve real world problems, the machine needs to be equipped with adequate processing power. To ensure better efficiency and less time consumption, multi-core high performing GPUs and similar processing units are required. These processing units are costly and consume a lot of power. Industry level deep learning systems require high-end data centres and smart devices such as drones, robots and other mobile devices require small but efficient processing units. Thus, deploying deep learning solutions in the real world becomes a costly and power consuming affair.***In the proposed research program, three aspects of deep learning will be investigated to address the aforementioned challenges. Firstly, deep learning algorithms have proven to be error-resilient. Approximate computing is a great candidate for error-resilient deep learning algorithms. Secondly, inference operations can be performed with low precision and training processes can be handled with high precision. Multiple-precision implementation is helpful to efficiently support operations with multiple-precision requirements. Thirdly, high bandwidth memory (HBM) combined with processing-in-memory (PIM) can address the memory bandwidth challenge by relieving the memory bottleneck and reducing power consumption.***In this research program, the design of novel hardware processor architecture for deep learning applications will be investigated by proposing approximate multiple-precision arithmetic units to build basic processing elements and adopting HBM combined with PIM. In addition, approximate computing based methods will be investigated to support flexibility, sparsity, and training. The primary target of the proposed deep learning processor is to address cost-energy-performance issues. The outcome of this research program will significantly improve the performance and power efficiency of deep learning systems.