Programmable memory systems for manycore architectures

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Multicore chips dominate the computing spectrum, replacing uniprocessors throughout the desktop, server, and mobile markets. In the future, manufacturers promise to deliver manycore chips which integrate 100s of diverse compute processors. An on-chip memory hierarchy needs to be carefully designed to ensure that the compute units are kept busy. Current memory hierarchies are hardware-managed with fixed policies for data management. This rigidity doesn't dovetail with the complex access patterns in modern applications and it has become challenging to effectively supply data to the large number of cores in a timely manner.