Low power design and verification

低功耗设计与验证

• 批准号: 414162-2011
• 负责人: Veneris, Andreas
• 金额: $ 1.82万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Engage Grants Program
• 财政年份: 2011
• 资助国家: 加拿大
• 起止时间: 2011-01-01 至 2012-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=491700
• 关键词: Low; power; design; verification

The semiconductor industry has revolutionized our lives in many different ways. Electronic technology perform tasks that are essential for our day-to-day lives. The impact of such technology use has been positive in many metrics. This technological success can be attributed to the design of faster and smaller chips that can perform a varied range of functionalities. The adverse effect of this advancement is the increase in power consumption of the chip beyond acceptable limits. Therefore, for chip reliability issues, for portability, and also for environmental purposes, it becomes an urgent necessity to design semiconductor products that have low power consumption with no adverse effect on their performance. Thus low power design is now at the forefront in the design of high performance integrated circuits. Low power and, indeed, low energy design metholdologies are increasingly becoming the principal focus for current and future generation VLSI chips. This work will develop a novel algorithm that would enhance the power savings in chips, reduce design time and address numerous design complexities in today's computer-aided design (CAD) flow. The primary goal is to develop low power methodology for the next egneration chips that can support far more demanding applications while consume much less power.

半导体行业以许多不同的方式彻底改变了我们的生活。电子技术执行的任务对我们的日常生活至关重要。在许多指标中，这种技术的使用产生了积极的影响。这种技术上的成功可以归功于设计更快、更小的芯片，这些芯片可以执行各种功能。这种进步的不利影响是芯片的功耗增加超过可接受的限度。因此，为了芯片可靠性问题、便携性以及环境目的，迫切需要设计具有低功耗而对其性能没有不利影响的半导体产品。因此，低功耗设计现在处于高性能集成电路设计的最前沿。低功耗和低能耗设计方法正日益成为当前和下一代超大规模集成电路芯片的主要焦点。这项工作将开发一种新的算法，提高芯片的节能，减少设计时间，并解决当今计算机辅助设计（CAD）流程中的众多设计复杂性。主要目标是为下一代芯片开发低功耗方法，可以支持要求更高的应用，同时消耗更少的功率。