Low power design and verification

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The semiconductor industry has revolutionized our lives in many different ways. Electronic technology perform tasks that are essential for our day-to-day lives. The impact of such technology use has been positive in many metrics. This technological success can be attributed to the design of faster and smaller chips that can perform a varied range of functionalities. The adverse effect of this advancement is the increase in power consumption of the chip beyond acceptable limits. Therefore, for chip reliability issues, for portability, and also for environmental purposes, it becomes an urgent necessity to design semiconductor products that have low power consumption with no adverse effect on their performance. Thus low power design is now at the forefront in the design of high performance integrated circuits. Low power and, indeed, low energy design metholdologies are increasingly becoming the principal focus for current and future generation VLSI chips. This work will develop a novel algorithm that would enhance the power savings in chips, reduce design time and address numerous design complexities in today's computer-aided design (CAD) flow. The primary goal is to develop low power methodology for the next egneration chips that can support far more demanding applications while consume much less power.