Understanding the hardware-level requirements of deep learning algorithms

点击翻译按钮获取中文摘要

At the heart of every computing device, there are one or more processing cores that manipulate data values and move them among storage devices or devices that interact with the physical world such as displays, touch screens, and microphones. For the past several decades, core performance, that is the rate at which data values could be manipulated or moved around, has doubled every two years. This has enabled advances in application sophistication and breadth. However, in recent years, this performance trend has ceased as a result of fundamental shifts in semiconductors, the underlying manufacturing technology. One key direction to improve the performance of hardware devices in both data centers and mobile platforms is hardware accelerators. An accelerator is a piece of hardware able to perform the tasks required by a specific application with higher performance and energy efficiency. Specialized accelerators can offer large performance and energy benefits (100x-1000x). At the same time, machine-learning based applications are ushering a new era in computing. Unfortunately, these applications stress existing hardware systems and do require further performance to evolve. Accordingly the goal of the proposed research is to understand the compute and memory communication requirements of a subset of machine-learning algorithms. The results of this work will be used to steer further research and development in hardware to better suit the needs of machine-learning applications.