Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware

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Unprecedented advances in Integrated Circuit fabrication technology have given rise to the low-cost high-speed Internet, mobile computing, and unparalleled computing power that analyzes, manipulates and automates activity throughout the planet. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risk associated with each deployment has also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have emerged as a Programmable Platform of choice for many of these crucial applications. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip. Building applications on FPGA programmable platforms, however, requires specialized hardware design skills. Designers with these skills are far outnumbered by software designers. To enable software designers to take full advantage of the speed and low power provided by FPGA platforms, high-level synthesis (HLS) tools have emerged. With HLS, a software program is automatically synthesized to a hardware circuit, obviating the need for low-level hardware design. HLS tools have matured to the point that they can be effectively used for hardware design. However, a key obstacle to their widespread adoption is that there is no standard methodology that allow software engineers to understand, debug, and optimize the resulting hardware. The proposed research centers precisely on this current limitation of existing HLS methodologies. Hardware engineers are accustomed to low-level debugging using logic analyzers and waveform viewers. Software engineers, on the other hand, use software debuggers and profilers to improve the quality of their code. In this project, we will research and design a framework that allows a software engineer to analyze, debug and improve the speed and power characteristics of HLS-generated hardware using a software-like ecosystem.