Raising the Abstraction of Analysis, Debug and Optimization of High-Level Synthesis-Generated Hardware

提高高级综合生成硬件分析、调试和优化的抽象性

• 批准号: 447002-2013
• 负责人: Wilton, Steven
• 金额: $ 7.26万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Strategic Projects - Group
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=575265
• 关键词: Raising; Abstraction; Analysis; Debug; Optimization

Unprecedented advances in Integrated Circuit fabrication technology have given rise to the low-cost high-speed Internet, mobile computing, and unparalleled computing power that analyzes, manipulates and automates activity throughout the planet. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risk associated with each deployment has also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have emerged as a Programmable Platform of choice for many of these crucial applications. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip. Building applications on FPGA programmable platforms, however, requires specialized hardware design skills. Designers with these skills are far outnumbered by software designers. To enable software designers to take full advantage of the speed and low power provided by FPGA platforms, high-level synthesis (HLS) tools have emerged. With HLS, a software program is automatically synthesized to a hardware circuit, obviating the need for low-level hardware design. HLS tools have matured to the point that they can be effectively used for hardware design. However, a key obstacle to their widespread adoption is that there is no standard methodology that allow software engineers to understand, debug, and optimize the resulting hardware. The proposed research centers precisely on this current limitation of existing HLS methodologies. Hardware engineers are accustomed to low-level debugging using logic analyzers and waveform viewers. Software engineers, on the other hand, use software debuggers and profilers to improve the quality of their code. In this project, we will research and design a framework that allows a software engineer to analyze, debug and improve the speed and power characteristics of HLS-generated hardware using a software-like ecosystem.

集成电路制造技术的前所未有的进步催生了低成本的高速互联网、移动计算和无与伦比的计算能力，这些计算能力可以分析、操纵和自动化地球上的活动。然而，随着集成继续其指数级的进展，基础制造技术的复杂性、开发该技术所需的专业知识以及与每个部署相关的财务风险也以指数级的速度增长。现场可编程门阵列(FGA)已成为许多此类关键应用的可编程平台选择。可将现场可编程门阵列配置为实现任何电路，使设计人员能够立即测试设计，而不会产生生产完全定制芯片的成本、风险和延迟。 然而，在FPGA可编程平台上构建应用程序需要专门的硬件设计技能。拥有这些技能的设计师远远超过了软件设计师。为了使软件设计人员能够充分利用FPGA平台提供的速度和低功耗，高级综合(HLS)工具应运而生。利用HLS，软件程序被自动综合到硬件电路中，从而消除了对低层硬件设计的需要。HLS工具已经成熟到可以有效地用于硬件设计的程度。然而，广泛采用它们的一个关键障碍是没有标准的方法来允许软件工程师了解、调试和优化所产生的硬件。所提出的研究正是围绕着当前现有HLS方法的局限性展开的。硬件工程师习惯于使用逻辑分析仪和波形查看器进行低级调试。另一方面，软件工程师使用软件调试器和分析器来提高他们的代码质量。在这个项目中，我们将研究和设计一个框架，允许软件工程师使用类似软件的生态系统来分析、调试和改进HLS生成的硬件的速度和功率特性。