Digital-intensive clocking and data recovery circuits for low-power scalable wireline transceivers

适用于低功耗可扩展有线收发器的数字密集型时钟和数据恢复电路

• 批准号: 483881-2015
• 负责人: Shekhar, Sudip
• 金额: $ 5.76万
• 依托单位: University of British Columbia
• 依托单位国家: 加拿大
• 项目类别: Collaborative Research and Development Grants
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=618647
• 关键词: Digital; intensive; clocking; data; recovery

Globally, we are on the cusp of revolutionary changes in communications fueled by the use of high throughput computing based on datacenter computers on one side, and mobile computing platforms such as laptops, tablets and smartphones on the other. Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technologies accompanied by increasing complexity of integrated-circuits has led to fast and efficient computing systems. These platforms demand off-chip data bandwidth with extremely low power consumption in order to conserve power, posing significant design challenges. This collaborative project between UBC and Intel will focus on addressing these challenges.This proposed research aims to develop advanced wireline integrated circuits (ICs) for low-power transceivers. The work to be accomplished in this project primarily involves a mix of modelling, design and measurement work. The target application is next-generation wireline solutions and products for the industry such as MIPI M-PHY, next-generation PCIE and USB, etc.

在全球范围内，我们正处于通信革命性变革的风口浪尖，一方面是基于数据中心计算机的高吞吐量计算，另一方面是笔记本电脑、平板电脑和智能手机等移动的计算平台。互补金属氧化物半导体（CMOS）技术的积极缩放伴随着集成电路的日益增加的复杂性已经导致快速且高效的计算系统。这些平台要求片外数据带宽和极低的功耗以节省功耗，这带来了重大的设计挑战。UBC与Intel的合作项目将致力于解决这些挑战，旨在为低功耗收发器开发先进的有线集成电路（IC）。在这个项目中要完成的工作主要涉及建模，设计和测量工作的混合。目标应用是下一代有线解决方案和产品，如MIPI M-PHY，下一代PCIE和USB等。