Phase I: High-performance clock multiplier units

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Our team at UBC is developing a novel clock multiplier unit (CMU). Our system leverages a novel radio frequency shifter that was invented in our lab to develop a system with a smaller area, lower power consumption, and higher frequency than a typical CMU existing in the market. A key differentiation is to provide many outputs with fractional frequency shifts from the input. Our goals for this proposal are to develop an evaluation board that can automatically calibrate its performance based on the required clock multiplication factor, and demonstrate operation of the prototype over process, voltage, and temperature variations and long-term operation. These technical milestones were set based on feedback from companies that were interviewed and who indicated a need for a high-performance CMU within the microelectronics market for access, infrastructure and connectivity. The interviewed companies indicated their willingness to beta-test our prototype in an industrial setting following the successful completion of this I2I phase I, with a view to becoming an early adopter.