Integrated Circuits for Large Arrays

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Computing and data communications have changed the way we work, communicate, socialize, learn, and educate. To improve livelihoods and to solve most of the challenging problems humans face as a society, we need wireless connectivity, computing, and data-centers that can process massive amounts of data with sustainable power consumption. With the exponential scaling of complementary metal-oxide-semiconductor (CMOS) technology coming to an end due to physical and economic limitations in manufacturing, multi-core and inter-linked data processing and communication have risen to the fore. 5G cellular systems have currently adopted 10-100 of antenna arrays, called Massive MIMO (Multiple-Input Multiple-Output), to facilitate the data throughput demanded by communications and computing systems. Furthermore, the next-generation architecture is predicting the use of extremely-large antenna arrays, in hundreds to thousands, to meet the projected demand for high-speed connectivity. The design of these hardware systems has extremely large challenges, with 100-1000 of such antennas requiring synchronization and an ability to steer the signal with precise angles (beamforming). Our research will seek to design circuits and systems to solve two critical problems in such a network: (1) high-frequency clock generation, distribution, and synchronization between the antenna elements with low-power consumption; and (2) precise beamforming. A similar need to move a massive amount of data is also arising to facilitate large machine learning computing tasks, leading to the adoption of multiple accelerator chips, called chiplets, interconnected to each other. With many machine learning tasks relying on data-intensive deep neural networks, large arrays of chiplets are being envisioned to carry out such demanding tasks in the future. Beyond the data crunching carried out by the processing elements, a large amount of power will be consumed by interconnects handling the data movement in such large arrays, even acting as a show-stopper for many tasks. This research proposal will seek to design circuits and systems to solve the interconnect challenge between the large arrays of chiplets: (1) doubling the data throughput on the short-reach electrical wireline links without power overhead; and (2) reducing the power consumption of silicon photonics link so as to bring optics closer to the compute chiplets. The applicant's previous discovery grant laid the foundation for these objectives at the devices and circuits level. This proposal aims for significant power consumption reduction and throughput increase to realize large arrays. Canada is a hotbed for research in wireless communications and machine learning. Ensuring that we also remain ahead in the hardware research and development to support the next generation of cellular systems and machine learning acceleration will pave the way for highly valued jobs, technologies, and startups.