Systematic and Structural Methods for Post-Silicon Validation

在过去的十年里，保证电子电路和系统达到既定或隐含的目标的难度一直在不断增加。这主要是由于状态空间对不断增长的状态元素数量的指数依赖性，以及在功率和能量限制下促进性能改进所需的过多的时钟和电源域。通常采用预硅验证来确保设计与其规范之间的一致性。在试生产之前，可以测量的东西受到模拟时间和精度的限制，当置信度被认为足够时，就会发布用于制造的设计。制造测试专注于筛选每个制造器件中的物理缺陷；考虑到其参考是设计实现，制造测试不关心发现和识别已泄漏到硅原型的细微设计错误(或错误)。因此，在硅前阶段采用的验证任务继续在这些早期硅原型上进行，这一术语通常被称为硅后验证。*由于模拟比实际硅原型慢6到9个数量级，因此不可能预先计算黄金响应。再加上缺乏内部节点访问，这使得芯片后验证成为一个棘手的问题。此外，最先进的电路和系统可能会在一次实验中失败，并在随后的实验中正常运行。这是因为逃到硅原型上的细微设计错误通常会被不易重复的事件所激发。例如，它们可以由由异步接口和/或电路操作模式中的动态变化引起的罕见交互来触发，例如，响应于变化的工作负荷或环境条件来在功率与性能之间进行权衡。考虑到上述情况，研究能够帮助硅后验证任务的新的系统方法可以为更广泛的电子行业带来显著的好处，无论是生产率的提高，更重要的是最终产品的质量。*作为该研究计划的一部分，我们的目标是研究用于通用硅后验证系统的所有关键构建块的自动化方法：轨迹收集和分析、事件检测、硅后刺激的产生和应用以及覆盖率测量。所有这一切都将依赖于设计结构，而不是其功能。我们的立场是，结构化方法将提供急需的理论基础，这将促进自动化方法在整个半导体行业的无缝移植，以及对下一代集成电路的可扩展性，下一代集成电路预计将在运行时积极权衡功率和性能。**

The difficulty of guaranteeing that electronic circuits and systems meet the stated or implied goals has been continuously increasing over the past decade. This is mainly due to the exponential dependence of the state space on the growing number of state elements, as well as the excessively large number of clock and power domains needed to facilitate performance improvements under power and energy constraints. Pre-silicon verification is commonly employed to ensure the consistency between the design and its specification. Before tapeout what can be measured is limited by the simulation time and accuracy, and designs are released for manufacturing when the confidence level is deemed sufficient. Manufacturing test is focused on screening for physical defects in each fabricated device; considering that its reference is the design implementation, manufacturing test is not concerned with finding and identifying subtle design errors (or bugs) that have escaped to silicon prototypes. Thus the verification tasks employed during the pre-silicon phase continue on these early silicon prototypes, a term commonly referred to as post-silicon validation.***Because simulation is 6 to 9 orders of magnitude slower than the actual silicon prototype, it is not practically possible to compute golden responses a-priori. Together with the lack of internal node access, this makes post-silicon validation an intractable problem. Furthermore, state-of-the-art circuits and systems might fail in one experiment and operate correctly in the subsequent ones. This is because subtle design errors that escape to the silicon prototypes are often excited by not-easily-repeatable events. For example, they can be triggered by rare interactions caused by asynchronous interfaces and/or dynamic changes in the circuit's operating mode, e.g., for trading-off power vs performance in response to varying workload or environmental conditions. Considering the above, investigating new systematic approaches that can assist the post-silicon validation tasks can bring significant benefits to the broader electronics industry, in terms of both productivity gains and, more importantly, the quality of the final product.***As part of this research program, we aim to investigate automated methods for all the key building blocks of a general-purpose post-silicon validation system: trace collection and analysis, event detection, post-silicon stimuli generation and application, and coverage measurement. All of the above will rely on the design structure rather than its functionality. It is our position that a structural approach will provide the much-needed theoretical foundations, which will facilitate seamless portability of automated methods across the semiconductor industry, as well as scalability to the next-generation of integrated circuits which are expected to aggressively trade off power vs performance at run-time. **