Systematic and Structural Methods for Post-Silicon Validation

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The difficulty of guaranteeing that electronic circuits and systems meet the stated or implied goals has been continuously increasing over the past decade. This is mainly due to the exponential dependence of the state space on the growing number of state elements, as well as the excessively large number of clock and power domains needed to facilitate performance improvements under power and energy constraints. Pre-silicon verification is commonly employed to ensure the consistency between the design and its specification. Before tapeout what can be measured is limited by the simulation time and accuracy, and designs are released for manufacturing when the confidence level is deemed sufficient. Manufacturing test is focused on screening for physical defects in each fabricated device; considering that its reference is the design implementation, manufacturing test is not concerned with finding and identifying subtle design errors (or bugs) that have escaped to silicon prototypes. Thus the verification tasks employed during the pre-silicon phase continue on these early silicon prototypes, a term commonly referred to as post-silicon validation.***Because simulation is 6 to 9 orders of magnitude slower than the actual silicon prototype, it is not practically possible to compute golden responses a-priori. Together with the lack of internal node access, this makes post-silicon validation an intractable problem. Furthermore, state-of-the-art circuits and systems might fail in one experiment and operate correctly in the subsequent ones. This is because subtle design errors that escape to the silicon prototypes are often excited by not-easily-repeatable events. For example, they can be triggered by rare interactions caused by asynchronous interfaces and/or dynamic changes in the circuit's operating mode, e.g., for trading-off power vs performance in response to varying workload or environmental conditions. Considering the above, investigating new systematic approaches that can assist the post-silicon validation tasks can bring significant benefits to the broader electronics industry, in terms of both productivity gains and, more importantly, the quality of the final product.***As part of this research program, we aim to investigate automated methods for all the key building blocks of a general-purpose post-silicon validation system: trace collection and analysis, event detection, post-silicon stimuli generation and application, and coverage measurement. All of the above will rely on the design structure rather than its functionality. It is our position that a structural approach will provide the much-needed theoretical foundations, which will facilitate seamless portability of automated methods across the semiconductor industry, as well as scalability to the next-generation of integrated circuits which are expected to aggressively trade off power vs performance at run-time. **