Fault-Tolerant Computing for Machine Learning Applications

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Machine learning has been successfully used in consumer applications, such as image/speech recognition. In recent years there has been a growing interest for adoption of machine learning in autonomous systems. In order to achieve the goal of full autonomy, not only lifelong machine learning paradigm must come of age, but also its guaranteed operation on degradable hardware is a necessity. Motivated by the above, the aim of this project is to investigate how machine learning models can be adapted in a gracefully degradable manner in the presence of hardware faults that arise in--field. In the early stages of this research program it will be necessary to understand what is unique about how faulty hardware interacts with machine learning applications. In particular, in addition to the set of sequentially--redundant faults, i.e., faults that cannot be excited in any reachable state of digital hardware, machine learning applications are expected to give rise to a large set of application--redundant faults, i.e., faults that cannot affect an observable output under a given set of application constraints, e.g., model parameters during the inference phase. Furthermore, since most machine learning applications have a user--acceptable loss in prediction accuracy, it is equally important to understand which types of hardware faults produce a tolerable vs an intolerable loss in prediction accuracy. Subsequently we will focus on developing novel methods for in--field test, diagnosis and fault tolerance that are specific to the characteristics of machine learning workloads. For example, during the inference phase of machine learning application, if one of the operands for a hardware multiplier is a constant then many of the multiplier's internal nets will not be observable; hence the hardware faults on the respective nets will be tolerated. This simple observation can lead to in--depth investigations on how to re-map/re-schedule nodes/operations on the large number of multiplier blocks present in machine learning hardware in order to tolerate a set of known faults. Alternatively it is also worth investigating how to update the parameters of a machine learning model in order to bypass the faults, while guaranteeing a tolerable loss in prediction accuracy. On another line of thought, in reinforcement learning environments used for autonomous systems, one needs to ensure that learning can continue despite the presence of hardware faults. This raises the question whether the existing on-line learning algorithms can be redefined in order to ensure that model parameters can be adjusted not only to the unique operating environment but also to the faulty hardware. As summarized above, machine learning workloads bring new dimensions to the field of fault--tolerant computing. It is the main focus of this research program to investigate these new dimensions and develop fault- tolerant computing methods adaptable to a broad spectrum of hardware architectures.