Design techniques for three-dimensional integrated circuits challenges

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The ever growing need for more complex integrated circuit (IC) has been driven by the need of complex new products packing more features and requiring faster and lower power processing. Scaling down transistors and using larger dies have been able to keep up with the market demand in the past. However, we are fast approaching the limits of continuous device scaling for planar two-dimensional (2D) IC design. Using 2D integration technologies to implement nowadays complex chips is becoming very expensive and difficult to meet nowadays design challenges. ***Three-dimensional (3D) integrated circuit (IC) technology, wherein IC chips are stacked in vertical 3D architectures, has emerged as a complement to silicon transistor scaling to achieve higher level of integration. Moreover, heterogeneous 3D-IC systems that integrate multiple dies, each optimized using different technologies, will offer More-than-Moore solutions for higher integration densities, lower power consumption, and higher performance. One of the most popular technologies for implementing 3D-ICs is through-silicon via (TSV) fabrication, in which multi-chip integration is enabled using TSVs to provide the vertical interconnections between dies. TSVs are smaller than off-chip wires thereby avoiding the excessive delay limitations of bonding wires. They can be used for connecting devices that reside on different dies, inter-die communications, as well as clock and power distribution. ***Like any new technology and despite the tremendous advantages of 3D-IC, circuits designer are faced with new design challenges particularly for clock synchronization and power delivery. The main design challenges are related to delay through the TSVs, which are susceptible to process and temperature variations. In addition, the delay through a TSV can increase significantly due to open defects leading to significant skew in clock distribution networks. Moreover, cross-die process variation limits the slack time for both within die and die-to-die paths using TSVs, thus requiring a tight constraint on clock skew and jitter . Intra-die and inter-die power distribution is another major challenge in 3D-IC design. ***Moreover, accurate physical characterization of TSVs represents a tremendous challenge for analog designer and an optimized layout technique is necessary to fully benefit from the advanced technology.***As a result to fully enjoy the merit of 3D-IC technology, the objective of this proposal is to develop novel digital, analog and mixed signal circuit design and system techniques to address the challenges of 3D integrations.