Design techniques for three-dimensional integrated circuits challenges

应对三维集成电路挑战的设计技术

• 批准号: RGPIN-2017-04292
• 负责人: ElSankary, Kamal
• 金额: $ 1.75万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=710467
• 关键词: Design; techniques; three; dimensional; integrated

The ever growing need for more complex integrated circuit (IC) has been driven by the need of complex new products packing more features and requiring faster and lower power processing. Scaling down transistors and using larger dies have been able to keep up with the market demand in the past. However, we are fast approaching the limits of continuous device scaling for planar two-dimensional (2D) IC design. Using 2D integration technologies to implement nowadays complex chips is becoming very expensive and difficult to meet nowadays design challenges. Three-dimensional (3D) integrated circuit (IC) technology, wherein IC chips are stacked in vertical 3D architectures, has emerged as a complement to silicon transistor scaling to achieve higher level of integration. Moreover, heterogeneous 3D-IC systems that integrate multiple dies, each optimized using different technologies, will offer More-than-Moore solutions for higher integration densities, lower power consumption, and higher performance. One of the most popular technologies for implementing 3D-ICs is through-silicon via (TSV) fabrication, in which multi-chip integration is enabled using TSVs to provide the vertical interconnections between dies. TSVs are smaller than off-chip wires thereby avoiding the excessive delay limitations of bonding wires. They can be used for connecting devices that reside on different dies, inter-die communications, as well as clock and power distribution. Like any new technology and despite the tremendous advantages of 3D-IC, circuits designer are faced with new design challenges particularly for clock synchronization and power delivery. The main design challenges are related to delay through the TSVs, which are susceptible to process and temperature variations. In addition, the delay through a TSV can increase significantly due to open defects leading to significant skew in clock distribution networks. Moreover, cross-die process variation limits the slack time for both within die and die-to-die paths using TSVs, thus requiring a tight constraint on clock skew and jitter . Intra-die and inter-die power distribution is another major challenge in 3D-IC design. Moreover, accurate physical characterization of TSVs represents a tremendous challenge for analog designer and an optimized layout technique is necessary to fully benefit from the advanced technology. As a result to fully enjoy the merit of 3D-IC technology, the objective of this proposal is to develop novel digital, analog and mixed signal circuit design and system techniques to address the challenges of 3D integrations.

对更复杂的集成电路（IC）的不断增长的需求是由包装更多特征并且需要更快和更低功率处理的复杂新产品的需求驱动的。过去，缩小晶体管尺寸和使用更大的管芯能够跟上市场需求。然而，我们正在快速接近平面二维（2D）IC设计的连续器件缩放的极限。使用2D集成技术来实现当今复杂的芯片变得非常昂贵并且难以满足当今的设计挑战。 三维（3D）集成电路（IC）技术（其中IC芯片堆叠在垂直3D架构中）已成为硅晶体管缩放的补充，以实现更高水平的集成度。此外，集成多个管芯的异构3D-IC系统（每个管芯使用不同的技术进行优化）将为更高的集成密度、更低的功耗和更高的性能提供比摩尔更高的解决方案。用于实现3D-IC的最流行的技术之一是硅通孔（TSV）制造，其中使用TSV来提供管芯之间的垂直互连以实现多芯片集成。TSV小于芯片外引线，从而避免了接合引线的过度延迟限制。它们可用于连接位于不同芯片上的器件、芯片间通信以及时钟和电源分配。 与任何新技术一样，尽管3D-IC具有巨大的优势，但电路设计人员仍面临着新的设计挑战，特别是在时钟同步和电源传输方面。主要的设计挑战与TSV的延迟有关，TSV易受工艺和温度变化的影响。此外，由于开路缺陷导致时钟分布网络中的显著偏斜，通过TSV的延迟可能显著增加。此外，跨管芯工艺变化限制了使用TSV的管芯内路径和管芯到管芯路径两者的松弛时间，因此需要对时钟偏斜和抖动的严格约束。管芯内和管芯间功率分配是3D-IC设计中的另一个主要挑战。 此外，TSV的精确物理特性对模拟设计人员来说是一个巨大的挑战，需要优化的布局技术才能充分受益于先进的技术。 因此，为了充分享受3D-IC技术的优点，本提案的目标是开发新的数字、模拟和混合信号电路设计和系统技术，以应对3D集成的挑战。