Mirrored Memristor Crossbar Array for Digital and Analog Implementation of Computer Arithmetic and, Spiking Neural Networks

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Memristor has the potential to enhance or augment several areas of integrated circuit design, computing and application. Recent progress in the design and fabrication of Memristor devices will enable them to be a core enabling technology for future affordable integrated circuits that need to be scalable, energy-efficient and reconfigurable. A Memristor's compatibility with CMOS structures make them an ideal device for various diverse applications. These include: logic operations, neuromorphic devices for high speed one and two-dimensional digital signal processing (DSP) with low power consumption, non-volatile memory, analogue electronics, and reconfigurable circuits and hardware that can learn and adapt autonomously. Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic and in-memory calculation applications.***The objectives of the proposed research are :***(a) To further develop the state-of-the-art Memristive based architectures and circuits for applications on digital design, finite field multipliers, computer arithmetic, neural networks, digital filters, few to mention. To further explore the design of arithmetic circuits using Continuous Valued Number System (CVNS) developed by the applicant and his students using Memristors for the design of a fully analogue neural network. We plan to develop an area-efficient Mirrored Memristive Crossbar Architecture by either eliminating feedback and/or reducing the number of transistors required.***(b) Spiking Neural Networks (SNNs) have emerged recently with a good potential for a wide ranges of applications like pattern recognition, clustering etc. It has been demonstrated that these networks can closely resemble some of the activities and function of the brain. There are many models reported in the literature that precisely define behavior and the functionality of their neurons. These models are mostly very complicated for practical implementation. We shall work to develop an accurate and efficient model for the digital implementation of SNNs which closely approximate models presented in the literature. We would look at the trade off for resource requirements versus higher accuracy that enable the designer to choose the model that fit his/her application. We shall also investigate novel ways of training SNNs through Spike Time Dependent Plasticity (STDP) methods for applications, such as, pattern recognition. We shall try to develop a Memrisor based digital implementation of SNNs for pattern recognition applications. The Memristor is being regarded as the viable technology for nano electronic circuits and a future replacement for many CMOS devices. Research in this area is very important for Canada to be competitive in the evolving world economy. Furthermore, this research will lead to competitive low-cost, low-power, high-speed and area-efficient computer arithmetic, and DSP algorithms and reconfigurable architectures that enable synergy.