Next Generation Field-Programmable Gate-Array Computer-Aided Design Tools based on Machine Learning

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***Compile times for Field Programmable Gate Array (FPGA) Computer-Aided Design (CAD) tools can be on the order of hours or even days for the largest, most complex designs. Excessive runtimes not only adversely impact engineering productivity and costs, they act as a serious impediment to the adoption of FPGAs by software developers who are used to compilation times of seconds or minutes. ******Recent advances in machine learning and deep learning offer fresh paradigms to revise or completely redesign traditional FPGA CAD algorithms and tools. Accordingly, the overarching goal of this research program is to develop a smart FPGA CAD flow. This work leverages machine learning, deep learning, modern optimization algorithms, and scalable parallelization to minimize the runtimes for key CAD steps in the flow and the total number of times these steps must be performed. ******As Place-and-Route (Pable for modern 2D and 2.5D FPGA devices, 3) combining the modular placement flow with a machine-learning framework to automatically construct the most appropriate placement strategy based on features of the circuit to be mapped onto the FPGA, 4) development of a smart detailed router that uses deep learning to guide the router to avoid excessive congestion thus improving runtime and solution quality, 5) development of machine-learning and deep-learning models to assist the technology (dependent) mapping stage to assess how local mapping decisions will impact subsequent solution quality, and 6) development of smart machine-learning and deep-learning models to assist in parameter selection, and the determination of circuit similarity methods so that past solutions for similar designs can be leveraged for new designs. ******The proposed research program will improve FPGA technology by making FPGAs easier to use by reducing compilation times and improving solution quality, and will bring a deeper understanding to how evolving machine learning and deep learning algorithms and methods will not only provide desired predictions or solutions to complex FPGA CAD problems, but will also enable FPGA CAD tools to learn from past design experiences to improve decision making, and hence performance, over time. The overall significance of this work will be to provide FPGA vendors and users with scalable, intelligent FPGA CAD tools that can produce high-quality solutions, while avoiding excessive runtimes. *****************