Placement and routing for video Codec applications running on modern FPGAs

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Each day, YouTube viewers alone watch almost 5 billion videos. Moreover, it is estimated that almost 64% of**all internet traffic is video content, with this number expected to rise to 80% by 2019. Both video encoding and**video compression are key enabling technologies in this context. Not only do they allow video to be delivered**in smaller bundles requiring less bandwidth and less storage, they also make it possible to provide many more**individuals with access to video content. With ever expanding display resolutions and evolving compression,**there is a need for high performance, low cost, reprogrammable hardware architectures that can be upgraded**quickly. Field Programmable Gate Arrays (FPGAs) are well suited to meet these needs. FPGAs blend the**benefits of both software and hardware, providing huge power, area, and performance benefits over software,**yet they can be reprogrammed cheaply to meet the requirements of many video and image processing**applications. In this proposal, we will explore ways of mapping video processing applications onto a modern**FPGA device to achieve maximum performance from the application. In particular, several tools will be**developed to help during the placement phase of the mapping process. These tools will consist of optimizations**suitable for placing the functional blocks in a design onto legal locations on an FPGA in a way that reduces**wirelength and congestion, and improves timing. We will target two types of FPGA architectures suitable for**meeting the requirements of video applications: one that contains all of the hardware resources on a single die,**and another that contains these resources on three dies. The resulting tools will help to support FPGA-based**video and image processing applications.