Placement and routing for video Codec applications running on modern FPGAs

现代 FPGA 上运行的视频编解码器应用的布局和布线

• 批准号: 530734-2018
• 负责人: Grewal, Gary
• 金额: $ 1.82万
• 依托单位: University of Guelph
• 依托单位国家: 加拿大
• 项目类别: Engage Grants Program
• 财政年份: 2018
• 资助国家: 加拿大
• 起止时间: 2018-01-01 至 2019-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=652468
• 关键词: Placement; routing; video; Codec; applications

Each day, YouTube viewers alone watch almost 5 billion videos. Moreover, it is estimated that almost 64% of**all internet traffic is video content, with this number expected to rise to 80% by 2019. Both video encoding and**video compression are key enabling technologies in this context. Not only do they allow video to be delivered**in smaller bundles requiring less bandwidth and less storage, they also make it possible to provide many more**individuals with access to video content. With ever expanding display resolutions and evolving compression,**there is a need for high performance, low cost, reprogrammable hardware architectures that can be upgraded**quickly. Field Programmable Gate Arrays (FPGAs) are well suited to meet these needs. FPGAs blend the**benefits of both software and hardware, providing huge power, area, and performance benefits over software,**yet they can be reprogrammed cheaply to meet the requirements of many video and image processing**applications. In this proposal, we will explore ways of mapping video processing applications onto a modern**FPGA device to achieve maximum performance from the application. In particular, several tools will be**developed to help during the placement phase of the mapping process. These tools will consist of optimizations**suitable for placing the functional blocks in a design onto legal locations on an FPGA in a way that reduces**wirelength and congestion, and improves timing. We will target two types of FPGA architectures suitable for**meeting the requirements of video applications: one that contains all of the hardware resources on a single die,**and another that contains these resources on three dies. The resulting tools will help to support FPGA-based**video and image processing applications.

每天，仅YouTube观众就观看了近50亿个视频。此外，据估计，几乎**所有的互联网流量中有80%是视频内容，预计到2019年这一数字将上升到80%。在这方面，视频编码和**视频压缩都是关键的使能技术。它们不仅允许**以更小的捆绑包提供视频**，需要更少的带宽和存储空间，而且还使更多**个人能够访问视频内容。随着不断扩展的显示分辨率和不断发展的压缩，**需要高性能、低成本、可重新编程的硬件架构，这些硬件架构可以**快速升级。现场可编程门阵列(现场可编程门阵列)非常适合满足这些需求。现场可编程门阵列融合了软件和硬件的**优势，与软件相比提供了巨大的功率、面积和性能优势**但它们可以廉价地重新编程，以满足许多视频和图像处理**应用的要求。在本计划中，我们将探索将视频处理应用程序映射到现代**FPGA设备上的方法，以实现应用程序的最高性能。特别是，将**开发几个工具，以便在测绘过程的安置阶段提供帮助。这些工具将包括**适合于将设计中的功能块以减少**有线长度和拥塞并改善计时的方式放置在FPGA上的合法位置的优化**。我们将针对两种适合**满足视频应用需求的FPGA架构：一种包含单个裸片上的所有硬件资源**，另一种包含三个裸片上的所有硬件资源。由此产生的工具将有助于支持基于FPGA的**视频和图像处理应用程序。