Next Generation Field-Programmable Gate-Array Computer-Aided Design Tools based on Machine Learning

对于最大、最复杂的设计，现场可编程门阵列（FPGA）计算机辅助设计（CAD）工具的编译时间可以是几个小时甚至几天。过多的运行时间不仅会对工程生产力和成本产生不利影响，而且会严重阻碍软件开发人员采用FPGA，因为他们习惯于数秒或数分钟的编译时间。 机器学习和深度学习的最新进展为修改或完全重新设计传统的FPGA CAD算法和工具提供了新的范例。因此，本研究计划的总体目标是开发智能FPGA CAD流程。这项工作利用机器学习、深度学习、现代优化算法和可扩展的并行化来最大限度地减少流程中关键CAD步骤的运行时间以及必须执行这些步骤的总次数。 作为地点和路线（适用于现代2D和2.5D FPGA器件，3）将模块化布局流程与机器学习框架相结合，以基于要映射到FPGA上的电路的特征自动构建最合适的布局策略，4）开发智能详细路由器，该路由器使用深度学习来指导路由器避免过度拥塞，从而提高运行时间和解决方案质量，5）开发机器学习和深度学习模型，以帮助技术（依赖）映射阶段评估本地映射决策将如何影响后续解决方案质量，以及6）开发智能机器学习和深度学习模型，以帮助参数选择，并确定电路相似性方法，以便可以利用类似设计的过去解决方案进行新设计。 拟议的研究计划将通过减少编译时间和提高解决方案质量使FPGA更易于使用来改进FPGA技术，并将更深入地了解不断发展的机器学习和深度学习算法和方法如何不仅为复杂的FPGA CAD问题提供所需的预测或解决方案，而且还将使FPGA CAD工具能够从过去的设计经验中学习，以改善决策。从而提高性能。这项工作的总体意义将是为FPGA供应商和用户提供可扩展的智能FPGA CAD工具，这些工具可以产生高质量的解决方案，同时避免过多的运行时间。

Compile times for Field Programmable Gate Array (FPGA) Computer-Aided Design (CAD) tools can be on the order of hours or even days for the largest, most complex designs. Excessive runtimes not only adversely impact engineering productivity and costs, they act as a serious impediment to the adoption of FPGAs by software developers who are used to compilation times of seconds or minutes. Recent advances in machine learning and deep learning offer fresh paradigms to revise or completely redesign traditional FPGA CAD algorithms and tools. Accordingly, the overarching goal of this research program is to develop a smart FPGA CAD flow. This work leverages machine learning, deep learning, modern optimization algorithms, and scalable parallelization to minimize the runtimes for key CAD steps in the flow and the total number of times these steps must be performed. As Place-and-Route (Pable for modern 2D and 2.5D FPGA devices, 3) combining the modular placement flow with a machine-learning framework to automatically construct the most appropriate placement strategy based on features of the circuit to be mapped onto the FPGA, 4) development of a smart detailed router that uses deep learning to guide the router to avoid excessive congestion thus improving runtime and solution quality, 5) development of machine-learning and deep-learning models to assist the technology (dependent) mapping stage to assess how local mapping decisions will impact subsequent solution quality, and 6) development of smart machine-learning and deep-learning models to assist in parameter selection, and the determination of circuit similarity methods so that past solutions for similar designs can be leveraged for new designs. The proposed research program will improve FPGA technology by making FPGAs easier to use by reducing compilation times and improving solution quality, and will bring a deeper understanding to how evolving machine learning and deep learning algorithms and methods will not only provide desired predictions or solutions to complex FPGA CAD problems, but will also enable FPGA CAD tools to learn from past design experiences to improve decision making, and hence performance, over time. The overall significance of this work will be to provide FPGA vendors and users with scalable, intelligent FPGA CAD tools that can produce high-quality solutions, while avoiding excessive runtimes.