An Intelligent, Parallel Framework for Field-Programmable Gate-Array Placement and Routing

点击翻译按钮获取中文摘要

Since their inception circa 1984, Field Programmable Gate Arrays (FPGAs) have seen an enormous growth in usage because they can dramatically reduce design turn-around time and manufacturing costs for prototype circuits and small to high-volume products. This is made possible by the availability of reconfigurable logic blocks, macro blocks, and programmable interconnections on a FPGA. It has been estimated that the world-wide FPGA market will reach $10 billion by 2016, with communication, automotive, medical, computer storage, military and wireless all important end markets. However, as the feature size continues to shrink and device capacity continues to increase in modern FPGAs, the design-automation industry is facing an old problem: the time spent for placement and routing is still dominating the FPGA compilation process. While current placement and routing tools produce quality solutions, compile times can be on the order of hours or even days for the largest designs. Long run times not only adversely impact engineering productivity and costs, they act as a serious impediment to the adoption of FPGAs by software developers who are used to compilation times of seconds or minutes. The primary goal of this research proposal is to develop an intelligent, parallel framework that can help a designer reduce the amount of time spent compiling circuits for FPGAs by performing placement and routing more efficiently and intelligently. The novelty of this proposal lies in combining state-of-the-art machine-learning and data-mining techniques with innovative parallel placement and routing methods running on multicore and many-core parallel architectures. A key feature of the proposed framework is its ability to learn from past placement and routing problems to more effectively and efficiently solve future placement and routing problems. The overall significance of this work will be to provide Canadian industry with scalable, parallel FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times. The resulting tools will help reduce the design cycle time and, consequently, design cost. Both design time and design cost are very important considerations for companies manufacturing electronic products based on FPGAs.