Nano-templated III-Vs on silicon for silicon photonics

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Direct hetero-epitaxial growth of III-V light emitting materials on Si (100) can provide the obvious solution to integrated Si photonics (SiP). However, the large lattice constant mismatch between Si and typical III-V materials make this process very challenging. Current approaches use miscut substrates, which are incompatible with industry standard CMOS processes. Moreover the thick buffer required to decrease dislocation density compromises optical coupling between the gain region and underlying Si waveguide structures. Our objectives are two-fold: (a) to demonstrate a suitable approach for growing III-V materials directly on Si (100) using nanoscale template "nucleation layer" technology, and (b) demonstrate high quality structures built on the nucleation layer structures, such that the III-V gain region lies proximate to the Si substrate plane. Such technology would provide full wafer-scale active photonics, with excellent low loss optical coupling implemented on Si (100), to enable an economical monolithic integration compatible with existing CMOS technology. Numerical models for optical coupling between the gain region and underlying Si waveguide structures will be developed to optimize the design of structures. If we can successfully develop this technology for our partner CISCO, it will enable them to dramatically reduce costs for datacomm systems and have a profound potential benefit for job and wealth creation here in Canada.