Energy-efficient high-density wired communication links

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Scaling of integrated-circuit (IC) process technologies has enabled orders-of-magnitude increases in the processing capabilities of microprocessors and graphics processing units. Input/output (I/O) data rates per lane and aggregate data rates have also increased. Up until the early 2000s, research was focused on increasing performance, with little regard for power dissipation. Today, due to physical limitations on the peak power density of ICs, emphasis on high-performance mobile computing, the high cost of cooling large computing infrastructure (i.e, data centres), and the increased concern over energy use and carbon footprint, energy efficiency trumps performance as the primary specification. A key enabler of efficiency is the "energy proportional" computation paradigm in which power dissipation must scale down during intervals of reduced activity in processors and I/O links. Through approaches such as clock-gating and dynamic voltage and frequency scaling, processors are moving toward the goal of energy proportionality. However, I/O links are lagging in this regard despite recent focus on energy proportional I/O links from a few groups. This proposal is aimed at circuit- and system-level improvements to the IC implementation of I/O systems with the goal of enabling energy proportionality in short-reach optical and electrical links. Investigations of burst-mode and gear-shifting approaches for transmitters and receivers have the potential to greatly reduce average power dissipation in I/O systems operating with time-varying bandwidth requirements. The outcomes of this proposal have can benefit a number of IC design companies having operations in Canada. These companies are part of a > 100 billion dollar per year industry, for which I/O is an enabling technology. The research activities in this proposal will provide excellent training for nine graduate students as they advance through all stages of mixed-signal IC design, gaining expertise in the use of industry-grade design tools, design methodology, design for test, and measurement practices.