Energy-efficient high-density wired communication links

集成电路 (IC) 工艺技术的扩展使得微处理器和图形处理单元的处理能力得到了数量级的提高。每通道的输入/输出 (I/O) 数据速率和聚合数据速率也有所增加。直到 2000 年代初，研究都集中在提高性能上，而很少考虑功耗。如今，由于 IC 峰值功率密度的物理限制、对高性能移动计算的重视、冷却大型计算基础设施（即数据中心）的高成本以及对能源使用和碳足迹的日益关注，能源效率取代了性能成为主要规格。效率的关键推动因素是“能量比例”计算范例，其中功耗必须在处理器和 I/O 链路活动减少的时间间隔内按比例降低。通过时钟门控、动态电压和频率缩放等方法，处理器正在朝着能量比例的目标迈进。然而，尽管最近有几个小组关注能量比例 I/O 链路，但 I/O 链路在这方面仍然落后。 该提案旨在对 I/O 系统的 IC 实现进行电路和系统级改进，目标是在短距离光和电链路中实现能量比例。对发射器和接收器的突发模式和换档方法的研究有可能大大降低具有时变带宽要求的 I/O 系统的平均功耗。 该提案的结果可以使许多在加拿大开展业务的 IC 设计公司受益。这些公司属于每年价值超过 1000 亿美元的行业，而 I/O 是该行业的一项支持技术。 该提案中的研究活动将为九名研究生提供出色的培训，帮助他们完成混合信号 IC 设计的所有阶段，获得使用工业级设计工具、设计方法、测试设计和测量实践的专业知识。

Scaling of integrated-circuit (IC) process technologies has enabled orders-of-magnitude increases in the processing capabilities of microprocessors and graphics processing units. Input/output (I/O) data rates per lane and aggregate data rates have also increased. Up until the early 2000s, research was focused on increasing performance, with little regard for power dissipation. Today, due to physical limitations on the peak power density of ICs, emphasis on high-performance mobile computing, the high cost of cooling large computing infrastructure (i.e, data centres), and the increased concern over energy use and carbon footprint, energy efficiency trumps performance as the primary specification. A key enabler of efficiency is the “energy proportional” computation paradigm in which power dissipation must scale down during intervals of reduced activity in processors and I/O links. Through approaches such as clock-gating and dynamic voltage and frequency scaling, processors are moving toward the goal of energy proportionality. However, I/O links are lagging in this regard despite recent focus on energy proportional I/O links from a few groups. This proposal is aimed at circuit- and system-level improvements to the IC implementation of I/O systems with the goal of enabling energy proportionality in short-reach optical and electrical links. Investigations of burst-mode and gear-shifting approaches for transmitters and receivers have the potential to greatly reduce average power dissipation in I/O systems operating with time-varying bandwidth requirements. The outcomes of this proposal have can benefit a number of IC design companies having operations in Canada. These companies are part of a > 100 billion dollar per year industry, for which I/O is an enabling technology. The research activities in this proposal will provide excellent training for nine graduate students as they advance through all stages of mixed-signal IC design, gaining expertise in the use of industry-grade design tools, design methodology, design for test, and measurement practices.