Toward a Hardware Architecture for Belief-Desire-Intention-based Agents

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With the current wide availability of robotic platforms and the operating systems to support them, it is now possible to implement their control using high-level plan monitoring and execution systems such as agent frameworks that rely on the Belief-Desire-Intention (BDI) paradigm. BDI allows the developer of an autonomous system to focus on implementing the various short-term plans (Intentions) and long-term goals (Desires) that the system can execute in the current context of its perceptions (Beliefs), and the BDI engine can then select, execute and monitor the appropriate plan given the current context. BDI has mostly only been evaluated in the context of simulated or toy environments, and so the performance aspects, especially when embedded in the real world, has not been investigated much to our knowledge. In particular, it is unknown what the actual bottlenecks in the execution of the BDI cycle are, and so what are the opportunities for hardware acceleration to address those bottlenecksToward this goal, we want to research the design of hardware architectures specifically suited for BDI systems. Whilst deep learning thrives on the super-pipelined, highly parallel fabric of GPUs, an ideal architecture for BDI has not been found. Our hypothesis is that this will require highly heterogeneous processing, interconnected with a memory hierarchy that reflects the data structures and access patterns representative of BDI implementations.We will set up a profiling system that allows us to instrument representative BDI implementations, and design strategies for automatically deriving hardware architectures that reflect the gathered profiles (through a combination of High Level Synthesis tools and custom hardware code generators). For each architecture, we will evaluate performance and power consumption for the set of BDI applications and assess bottlenecks.