Analog Integrated Circuits in Nano-scale Emerging Technologies

纳米级新兴技术中的模拟集成电路

• 批准号: RGPIN-2016-05681
• 负责人: ElMasry, Ezz
• 金额: $ 2.26万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751583
• 关键词: Analog; Integrated; Circuits; Nano; scale

The classical planar CMOS transistor is reaching its scaling limits and “end-of-roadmap”. This has been concluded as a result of the following shortcomings of nano-scale planar MOSFETs: undesirable process variations, short channel effects, high drain induced barrier lowering, substantial leakage currents, lower intrinsic gain, lower output impedance, lower dynamic range, poorer device matching and threshold voltage fluctuations. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to nano-scale integrated circuits performance. Therefore, robust RF, analog and mixed-signal circuits using nano-scale bulk CMOS devices beyond the 32-nm node may no longer be practical. Alternative devices that have been investigated are the FinFETs. These devices are suitable candidates to replace planar MOSFETs in technology below 32-nm node. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and calls them “Advanced non-classical CMOS devices”. While the advantages of the FinFETs started to reap its fruit for digital circuits, adopting FinFETs for analog circuits leave the analog designer with new challenges and problems to tackle. Therefore, new specialized circuits design techniques and new architectures need to be developed. This provides the motivation for this research project. We will explore the use of FinFETs to develop high performance, low-voltage and low-power analog and mixed-signal integrated circuits design techniques for future nano-scale systems implementation. Achieving the proposed objectives would advance the analog circuit designer knowledge. The principal beneficiaries of this work will be researchers and designers working on System-on-Chip solutions for telecommunication, biomedical and sensor applications. Where the need for low-cost, wearable/implantable monitoring devices using indirect measurement techniques becomes extremely useful in both monitoring and possibly keeping health costs down. Moreover, this research work has the potential to provide valuable intellectual property that can be used to develop useful applications for the scientific and industrial markets. Finally, the proposed research project represents a remarkable capacity to innovate; hence, it will be the subject for several prestigious journals, international conferences publications and possibly patents.

经典的平面CMOS晶体管正在达到其缩放极限和“路线图的终点”。这是由于纳米级平面MOSFET的以下缺点而得出的结论：不期望的工艺变化、短沟道效应、高漏极引起的势垒降低、大量漏电流、较低的固有增益、较低的输出阻抗、较低的动态范围、较差的器件匹配和阈值电压波动。这些非理想性最终会降低CMOS器件的性能，并对纳米级集成电路的性能构成严重威胁。因此，使用超过32 nm节点的纳米级体CMOS器件的鲁棒RF、模拟和混合信号电路可能不再实用。已经研究的替代器件是FinFET。这些器件是合适的候选人，以取代平面MOSFET的技术低于32纳米节点。国际半导体技术路线图（ITRS）认识到这些器件的重要性，并将其称为“先进的非经典CMOS器件”。 虽然FinFET的优势开始在数字电路中收获成果，但将FinFET用于模拟电路给模拟设计人员带来了新的挑战和问题。因此，需要开发新的专用电路设计技术和新的体系结构。这为本研究项目提供了动力。我们将探索使用FinFET开发高性能，低电压和低功耗的模拟和混合信号集成电路设计技术，为未来的纳米级系统的实施。 实现所提出的目标将提高模拟电路设计人员的知识。这项工作的主要受益者将是致力于电信、生物医学和传感器应用的片上系统解决方案的研究人员和设计人员。在需要低成本的情况下，使用间接测量技术的可穿戴/可植入监测设备在监测和可能降低健康成本方面变得非常有用。此外，这项研究工作有可能提供有价值的知识产权，可用于为科学和工业市场开发有用的应用。最后，拟议的研究项目代表了卓越的创新能力;因此，它将成为几个著名期刊，国际会议出版物和可能的专利的主题。