Low-voltage and low-power mixed-signal ICs in deep-submicron CMOS technology

点击翻译按钮获取中文摘要

Analog integrated circuits (IC's) designers have been forced, primarily by economics, to develop circuits using the dominant digital CMOS technologies. In CMOS the supply voltage continues to scale down below 1 V. Even if the process technology didn't require reduced supply voltages, the rapidly growing reliance on battery-powered microsystems (such as portable consumer electronics, computing devices, wireless communication systems, and biomedical implants) has led to an increase need for high performance ICs that operate under low supply voltage, consume low-power and capable of high frequency operation. On top of this continuous drive for performance improvement, there is also the continuing march of Moor's Law, which drives microsystems to be implemented in nanometer CMOS process. High performance analog circuits become increasingly difficult to implement in nano-scale CMOS due to the reduced intrinsic small signal gain and device headroom, making previously acceptable analog topologies and technologies become obsolete. Therefore, new specialized design techniques, new topologies and new architectures are needed. This provides the motivation for this research project. It explores low-voltage and low-power analog IC's design techniques and develops new high performance analog devices for future microsystems implementation.