Investigation of Nanoengineered III-V Buffer Layers for Hetero-integration on Silicon

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One of the most technically challenging and expensive aspects of silicon photonics for applications such as transceiver modules is the incorporation of a laser source. Difficulties include poor coupling of light from the laser chip to the silicon photonics chip, heat extraction from and temperature sensitivity of the laser device, cost of substrates used for the laser device, feedback sensitivity of the laser requiring incorporation of bulky optical isolators and lenses, and expensive packaging and specialized fabrication steps. All of these issues translate to a decreased yield, increased cost, and longer production time.Researchers at the University of Toronto, led by Prof. Harry Ruda, have pioneered and begun to demonstrate a technique by which single-crystal InGaAs with low defect density can be directly grown on a (100) silicon substrate. Here, in collaboration with Huawei Technologies, we propose to develop and optimize an approach based on leveraging nano-templating method to provide integration of the active III-V optical devices with Si passive optics as well as Si microelectronics. A successful development of the proposed technology will facilitate (i) realization of defect-free III-V regions required for high-performance opto-electronics applications (ii) close coupling between Silicon and III-V layers necessary for optical devices such as lasers with the III-V region as the active medium coupled to waveguides in Silicon. Further, dislocation-free hybrid growth envisaged here uses industry standard Si (100) as opposed to non-standard 6 degree miscut Si substrates, and dramatically enhances the ease of their incorporation into existing technology.