复杂纳米工艺导致电路性能严重偏差，对集成电路成品率产生显著影响。为了验证集成电路统计特性，传统方法采集“大数据”来分析，其代价越来越难以承受。近年来如何采用“小数据”而非“大数据”来获得高精度的统计分析成为集成电路分析国际前沿研究的新方向。本项目提出贝叶斯推断的思想，利用集成电路在设计与制造不同阶段的电路性能的相关性，将设计早期的数据作为先验知识，与后期的小数据进行融合，高精度地推断电路性能统计分布特性、制造工艺特性等，极大地降低集成电路分析验证的成本。现有贝叶斯推断电路分析方法仅能分析电路的单个连续型性能参数，在实际应用中具有局限性。本项目将发展针对离散型性能参数的贝叶斯推断及多个性能参数的贝叶斯推断新理论和新方法，并应用于高速互连误码率分析、集成电路参数成品率分析、老化分析以及化学机械抛光工艺建模等，为下一代纳米尺度集成电路设计与制造的分析、验证、测试建立基础性的理论框架和高效算法。

The severe process variations of the complex nanometer process technology cause the random variations of integrated circuit performance and the significant degradation of the chip yield. To validate the VLSI circuit performance considering process variation, a large number of data need to be collected by the traditional analysis approaches which result in computation explosion and can not be applied to stochastic analysis of real integrated circuits. How to analyze statistical performance using small data instead of big data has become a new research direction in the leading edge research for enhancing the chip yield. ..In this project, we propose a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon verification and post-silicon validation. The proposed BMF technique is motivated by the fact that today’s integrated circuits design cycle typically spans multiple stages. Our key idea is to reuse the simulation and/or measurement data collected at an early stage to facilitate efficient validation of integrated circuits with a minimal amount of data required at the late stage. Towards this goal, new Bayesian Model Fusion framework will be established to deal with discrete performance metric and multiple correlated performance metrics of integrated circuits, while only continuous performance metric and single performance metric have been established in the existing Bayesian Model Fusion methodology. The proposed new Bayesian Model Fusion framework will be employed to efficiently analyze four important industrial applications, including (1) efficient Bit Error Rate estimation for High-Speed Link, (2) efficient multivariate moment and yield estimation for Analog and Mixed-Signal Circuits, (3)Aging analysis of integrated circuits, (4) modeling of Chemical Mechanical Polishing of copper interconnect technology. Our preliminary results show that BMF is able to reduce the validation cost by 3~10x compared to other traditional methods. ..The proposed BMF technique provides a fundamental infrastructure that enables next-generation integrated design for nanoscale IC technology. It is expected to yield significant performance improvement for advanced electrical circuits in a broad range of applications, from consumer electronics to medical instruments. Hence, successful development of the proposed BMF framework will have both short-term and long-term impacts on the semiconductor industry.