三维集成电路的热、应力分析及协同物理设计研究

三维集成电路通过硅通孔（TSV）实现垂直方向的芯片堆叠，大幅提高芯片集成度，减少互连长度，提高芯片性能，并能实现不同工艺芯片集成，是延续摩尔定律的国际集成电路的重要发展方向。本课题针对三维集成电路中热、应力导致的电迁移、互连失效、性能下降等问题以及三维集成电路设计复杂度问题开展研究，1）提出了基于并行自适应有限元创新数学方法，建立全芯片三维集成电路的热分析、应力分析快速仿真方法，能够应用于指导物理设计的热分析、应力分析的快速模型；2）提出了TSV应力和热协同的物理设计方法；3）证明了TSV分配问题是NP完全问题，并提出了一种基于最短路径搜索、二分图匹配、最小费用最大流计算和后处理的硅通孔分配算法。这些新理论和新方法的研究将大幅提高三维集成电路设计和分析的效率，提升三维集成电路的性能和可靠性。本课题对推动我国开展国际前沿的三维集成电路设计方法研究和EDA技术开发具有重要理论价值和应用前景。

3D IC integration is an advanced technology which enables vertical integration of silicon dies forming a single 3D-IC stack. 3D IC ingegration can reduce interconnect wire length and achieve higher integration, higher performance and lower cost, even integration of dies with different process technologies. 3D IC manufactural technology is very promising and important for extending Moore's law. In this project, we focus on the study of thermal analysis and stress analysis and the complexity issues involved in the 3D IC physical design. We have proposed parallel adaptive Finite Element Method for the simulation and fast modeling of the thermal stresses of TSV based 3D ICs. We also proposed thermal stress driven 3D IC placement and routing methods. Finally we have proved the TSV assignment problem with more than two layer dies is NP complete. An integrated method which combines the Shortest Path Search, Bipartite Matching, Min Cost and Max Flow Calculation and Post Processing is proposed to achieve good quality results with reasonable running time when compared to the existing works. The proposed design methodologies are novel to 3D IC design area and quite useful for solving the complexity problem. The research results generated from this project is also very important to the development of 3D IC EDA tools in China.