高密度晶圆级芯片直接倒装互连高效精准一致创成关键技术研究

本项目针对高密度晶圆级芯片倒装需求，彻底摒弃回流焊工序，提出研究带六自由度对位偏差补偿的芯片直接倒装定位平台优化设计理论与方法，最终一步到位实现芯片-基板全方位对位偏差实时矫正；基于“进给-力觉”感知融合驱控一体化的交互设计思想，设计宏微跨尺度倒装键合装置，构建多传感器融合下的“位/力精密平滑切换”优化策略，实现键合机构位/力混合控制与芯片软着陆互连；开展芯片位姿偏差“像素-亚像素”智能复合自反馈模板匹配视觉检测算法研究，突破光学硬件及传统视觉算法性能的限制，实现芯片视觉检测速度精度的双重跃升；开展基于鲁棒输入整形抑振的快速滑模非线性控制及多维跨尺度高速协同微纳控制研究，从新的角度解决高密度晶圆级芯片倒装多维跨尺度的高速精密切换控制及协同微纳操作的问题。本项目研究成果可为晶圆级芯片直接倒装技术的实现提供坚实的理论支撑，对于我国实现高端半导体芯片封装装备的自主研发与应用具有重要的参考意义。

The newest wafer-level-flip-chip (WLFC) direct packaging technology abandons the traditional reflow soldering process and realizes chip-substrate interconnection by one step, which is the mainstream trend of current high-density wafer-level chip packaging. Aiming at the difficulty of fast precise positioning and precise operation of flip-chip packaging equipment under high dynamic conditions, this project innovatively proposes a WLFC direct packaging positioning stage with flexure spacial parallel nanopositioning mechanism, which can compensate all-directional alignment deviations; The aim of this project is to reveal the " Precision Smooth Switching of Position/Force" under multi-sensor fusion by studying the electro-magnetic-force coupling nonlinear dynamic behavior under multi-parameter time-varying conditions, smooth handover mechanism is intrinsically related to the interconnection of chip soft landing, then, an interactive design idea of "feed-force sense" perception fusion & driving-control integration is established and a macro-micro cross-scale flip-chip bonding execution mechanism is designed; A new principle of self-feedback template matching is proposed, and a new method of “pixel-sub-pixel” intelligent compound vision detection based on cross-entropy dissimilarity is constructed for improving the speed and accuracy simultaneously; Based on the piecewise optimal control strategy consist of robust input shaper, fast sliding mode controller, impedance controller and differential constrained linear filter, thus the problem of multi-dimensional and cross-scale high-speed cooperative micro/nano interconnection problem is solved from the proposed new perspective. The achieved results can provide support for the independent research and development of high-end semiconductor chip packaging equipment for our country, and have important theoretical and practical significance.