Memory Hierarchy in MIMD Multiprocessors

本课题组拟研究MIMD多处理器中存储器层级的管理。最近的技术爆炸已经允许在内存层次的许多级别中包含大而快速的存储器。在单处理器环境中很容易理解这种层次结构的管理，但是在多处理器系统中出现了新的挑战。其中一个挑战是缓存一致性问题。他们将继续之前在共享总线系统（用软件提示增强现有解决方案，评估特定应用）和互联系统（他们将模拟广泛的解决方案）中缓存一致性的研究。他们将把这些研究扩展到高性能系统中内存层次的设计和管理。这将包括多层缓存（架构选择、协议设计和评估）和并非所有级别都在虚拟内存概念下管理的系统（在编译器和程序员的协助下，在内存级别之间使用计划的数据传输）。最后，他们将尝试定性和定量地评估从传统真实缓存到使用虚拟地址缓存的架构的转换缓冲区位置的众多可能性。

The research team intends to study the management of the memory hierarchy in MIMD multiprocessors. The recent technological explosion has allowed the inclusion of large and fast memories in many levels of the memory hierarchy. The management of this hierarchy is quite well understood in a uniprocessor environment but newer challenges present themselves in a multiprocessor system. One of these challenges is the cache coherence problem. They will continue previous studies on cache coherence in shared-bus systems (enhancement of existing solutions with software hints, evaluation on specific applications) and in interconnected systems (they will model a wide spectrum of solutions). They will extend these studies with those pertaining to the design and management of the memory hierarchy in high-performance systems. This will include multilevel caches (architectural choices, design and evaluation of protocols) and systems where not all levels are managed under the virtual memory concept (use of planned transfers of data between memory levels with compiler and programmer assists). Finally, they will try to evaluate qualitatively and quantitatively the numerous possibilities for the location of the translation buffer from the conventional real caches to those architectures using virtual address caches.