Research Initiation: Testing and Fault Tolerance of MOSFET and MODFET Memories

本研究旨在通过仿真和实验研究，了解具有沟槽式电池电容的硅动态随机存取存储器（DRAM）等新型高密度高速存储技术的失效机制。GaAs（砷化镓）HEMT（高电子迁移率晶体管）SRAM（静态随机存取存储器）和CMOS（互补金属氧化物半导体）神经网络联想存储器。基于这种故障特征，Mazumder博士建议开发适当的测试方法。他的研究分为三个阶段。第一阶段研究了一种用于多兆硅DRAM的新型片上双纠错电路。该电路将纠正传统纠错电路无法纠正的双比特/字行软错误。在第二阶段，他正在开发高速GaAs HEMT静态RAM的全面故障模型和高效参数测试算法；并正在研究内置的自检电路来生成算法。第三个问题是如何测试神经网络联想记忆，并研究在存在错误组件和错误输入数据的情况下这种记忆的纠错能力。

This research is to understand, through simulation and experimental studies, the failure mechanisms of new high-density and high-speed memory technologies such as silicon DRAM's (dynamic random-access memory) with trench-type cell capacitor, GaAs (Gallium Arsenide) HEMT (High-Electron Mobility Transistor) SRAM's (static random-access memory) and CMOS (complementary metal oxide semiconductor) neural network associative memories. Based in this fault characterization, Dr. Mazumder proposes to develop appropriate test methodologies. His research is in three phases. The first phase investigates a new on-chip double-error correction circuit for the multi-megabit Silicon DRAM. This circuit will correct double-bit/word-line soft errors that cannot be corrected by conventional error correcting circuits. In the second phase, he is developing a comprehensive fault model and efficient parametric test algorithms for high-speed GaAs HEMT Static RAM; and is investigating built-in self-test circuits to generate the algorithms. The third problem is how to test neural network associative memories and a study of error correction capabilities of such memories in the presence of faulty components and erroneous input data.