Design and Analysis of High Performance Cache-coherent Multiprocessors Based on Shared Buses

共享内存多处理器系统中最重要的问题之一是所谓的内存延迟，它包括主内存访问时间和互连网络（in）争用。在并行计算机中引入高速内存作为一种提高系统性能的有效方法已被广泛接受。然而，多缓存会产生缓存一致性问题，为了使计算机正常工作，必须解决这个问题。传统的多处理器共享存储系统缓存一致性问题求解技术存在潜在的瓶颈问题，严重制约了多处理器系统的可扩展性。本课题研究基于高带宽、分组的分布式缓存一致性协议。切换 多个。总线INs。倍数的两种构型。在本研究中将考虑到：公交车的层次结构和同质单。水平多个总线。本文还研究了基于这两种结构的缓存协议的分析模型，以展示新协议的性能改进。因此，研究涉及(a)研究新协议的正确性和效率；(b)为这些系统发展分析模型；(c)基于不同应用软件的两种结构性能比较；(d)检查系统参数对系统性能的影响，包括总线数量、缓存块大小、层次结构中的层数以及每层连接到总线的模块数量。

One of the most essential issues in a shared memory multiprocessor system isthe so called memory latency that includes both the main memory access timeand the interconnection network (IN) contention. The introduction of cachememory into parallel computers has been widely accepted as an efficient way ofimproving the system performance. However, multicaches create a cachecoherence problem which must be solved in order for a computer to workcorrectly. Traditional solution techniques for the cache coherence problem inshared memory multiprocessor systems have a potential bottleneck problem whichsignificantly restricted the scalability of multiprocessor systems. This pasresearch project investigates new distributed cache coherence protocols basedon high bandwidth, packet.switched multiple.bus INs. Two configurations ofthe multiple.bus will be considered in this research: hierarchicalstructures of buses and homogeneous single.level multiple buses. It alsoinvestigates analytical models for the cache protocols based on the twostructures to show the performance improvement of the new protocols. Theresearch thus involves (a) study of the correctness and efficiency of the newprotocols; (b) development of analytical models for the systems; (c)performance comparison of the two structures based on different applicationsoftwares; (d) examination of the effects of system parameters on the systemperformance including number of buses, cache block size, number of levels in ahierarchy, and number of modules connected to a bus at each level.