Design of Fabrication of Electronic Neural Networks for Built-in Self-Repair of VLSI Chips with Embedded Logic Memory Arrays

这项研究是利用神经网络的组合优化能力来设计算法来解决IC芯片的修复问题。目前正在研究两类阵列修复问题。第一种是通过替换行和列来修复(如在存储器阵列中)。第二种是通过替换单个细胞来修复(如在脉动阵列和迭代逻辑中)。对阵列修复问题的理论模型进行了分析和仿真，以衡量神经修复算法的性能。将执行记忆、心动和迭代阵列的神经修复算法的电子神经网络正在设计和制造中。

This research is using the combinatorial optimization capabilities of neural networks to devise algorithms for solving repair problems in IC chips. Two classes of array repair problems are being examined. The first is repair by replacement of rows and columns (as in memory arrays). The second is repair by replacement of individual cells (as in systolic arrays and iterative logic). Theoretical models of array repair problems are being analyzed and simulated to measure the performance of neural repair algorithms. Electronic neural networks that will execute the neural repair algorithms for memory, systolic and iterative arrays are being designed and fabricated.