Research on Design Methodologies for High-Density, High- Performance, Wire-Dominated Chips and Multichip Modules

Kuh 这是一个与加州大学伯克利分校的联合项目。Kuh），加州大学圣巴巴拉分校（M。Marek-Sadowska）和加州大学圣地亚哥分校（C.- K. Cheng和T.C. Hu）。 集成电路（IC）设计现在主要是由导线，不能再被认为是完美的导体。 本研究的长期目标是找到一种新的CAD方法来设计高性能的大型和密集的电路，其中有很大一部分的物理布局所占用的导线。 正在开发新的算法，主要强调有效处理非常大的问题实例的能力。 这些算法包括扩展的平面规划的问题，如性能驱动的分区，时序仿真，包括传输线，时钟偏差优化，路由和压缩。 也正在开发的算法来解决跨越这些经典问题的边界，并探讨以前没有研究的依赖关系的问题。 这些研究的大部分都是高密度芯片和多芯片模块的高性能设计所共有的。

Kuh This a joint project with the UC at Berkeley (S. Kuh), UC at Santa Barbara (M. Marek-Sadowska) and UC at San Diego (C.-K. Cheng and T.C. Hu). Integrated circuit (IC) design is now dominated by wires which can no longer be considered as perfect conductors. The long term goal of this research is to find a new CAD methodology for designing high-performance large and dense circuits which have a large portion of the physical layout occupied by the wires. New algorithms with major emphasis on ability to handle efficiently very large problem instances are being developed. These include algorithms for the problem of extended floor-planning; such as, performance-driven partitioning, timing simulation including transmission lines, clock skew optimization, routing and compaction. Also being developed are algorithms to solve problems which span the boundaries of several of these classical problems and explore dependencies which were previously not studied. Much of this research is common to high performance design of both high-density chips and multichip modules.