RIA: Comprehensive BIST Methodology for Delay and Stuck-at Faults

这项研究致力于开发高效的内建自测试(BIST)方案，该方案既可以检测延迟，也可以检测故障。目标是合理的测试时间和最小的BIST硬件。这项研究有两个突破口。首先是对两种加权测试码生成器设计的探讨。四进制加权测试模式生成器被设计为伪随机测试的良好来源。另一种是生成时间相关测试码的算法，其方式是检测延迟故障所需的两个矢量是最佳的。其关键思想是使用权重来生成连续向量之间的相关性。其次，正在进行广泛的故障模拟，以开发用于测试模式生成器的错误模型以及复合故障模型。正在进行分析，以确定由于连续向量引起的误差之间的时间相关性，以及误差在空间上的分布。计划了基于该数据的压缩方案。

This research is on developing efficient Built-In-Self-Test (BIST) schemes which detect delay as well as stuck at faults. Goals are reasonable testing time and minimal BIST hardware. The research has two thrusts. First is exploration of two weighted test pattern generator designs. Quaternary weighted test pattern generators, are being designed to be a good source of pseudo-random tests. Another is an algorithm to generate temporally correlated test patterns in such a way that the two vectors required to detect delay faults are best. The key idea is that the weights are used to generate correlations between consecutive vectors. Second, extensive fault simulations are being performed to develop an error model for the test pattern generators, as well as a composite fault model. Analysis is being made to determine temporal correlation between errors due to consecutive vectors, and distribution of errors in space. Compression schemes based on this data are planned.