Error Detection and Recovery in High-Performance Fault-Tolerant Processor Systems Employing Caches

这是一个减轻使用缓存存储器的冗余计算机系统中瞬态故障影响的项目。冗余计算机系统通常采用投票电路作为处理器-存储器接口的一部分，以检查所有总线事务的一致性。如果使用了缓存内存，那么许多操作都不使用处理器-内存接口，因此可以逃避投票者的审查。在这个项目中，正在设计新的缓存协议，为冗余系统提供容错能力。新协议要求缓存控制器偶尔广播缓存线路的内容，并要求缓存控制器响应来自内存系统的请求以替换错误数据。该项目涵盖了容错缓存协议的开发、分析和应用。

Somani This is a project to mitigate the effects of transient faults in redundant computer systems that use cache memories. Redundant computer systems typically employ a voting circuit as part of the processor-memory interface to check for consistency in all bus transactions. If cache memories are used, many operations do not use the processor-memory interface, and so escape the scrutiny of the voter. In this project new cache protocols are being designed that provide for fault tolerance in redundant systems. The new protocols require the cache controllers to broadcast the contents of cache lines on occasion, and require cache controllers to respond to requests from the memory system to replace erroneous data. The project covers the development, analysis, and application of fault-tolerant cache protocols.