Analog VLSI Neural Network Employing A Novel Linear Synapse

这是SBIR关于神经网络（NN）突触设计的第二阶段研究。在第一阶段，该公司设计了一种新颖的突触电路，其线性范围是以前最先进电路的10倍，尺寸是以前电路的一半。同时，设计了一种基于神经网络的芯片。在第二阶段，该公司正在设计和测试剩余的网络元件，并改进突触。实现片上学习的全尺寸原型芯片，包含多达65万个突触正在开发中。该芯片设计使多个芯片相互连接，形成多层网络。此外，正在设计一个原型反向传播网络，该网络将在单个芯片上集成所有网络元素，并允许至少两个芯片互连。

This is SBIR Phase II research on designing a synapse for a neural network (NN). During Phase I the company devised a novel synapse circuit, which is linear over a range that is 10 times that of previous state-of-the-art circuits, and half the size of previous circuits. Also a NN for the chip was designed. During Phase II, the company is designing and testing the remaining network elements and improving the synapse. A full scale prototype chip that implements on-chip learning, and contains up to 650,000 synapses is being developed. The chip design enables interconnection of several chips in order to form a multi-layer network. In addition a prototype back propagation network which will integrate all network elements on a single chip and allows interconnection of at least two chips is being designed.