Improving the Performance of Digital Logic Simulation

这项研究是关于同步电路和异步电路的编译仿真。一种名为逆算法的数字逻辑模拟算法正在研究中。这是一个非常有效的算法，但能够模拟任何数字电路。目前正在对该算法进行基本扩展。这些包括单元和多延迟时序模型、具有未知值的逻辑模型、新的门、新的功能类型以及位并行模拟。此外，正在对其进行重新设计，以降低模拟的复杂性和模拟期间处理的事件数量。其他活动包括将现有模型扩展到多处理器实现，以及处理异步时序电路。人们正在探索将该算法应用于分层模拟和增量编译。

This research is on compiled simulation of synchronous and asynchronous circuits. A digital logic simulation algorithm, called the Inversion Algorithm, is being investigated. This is a very efficient algorithm, yet capable of simulating any digital circuit. Basic extensions are being made to the algorithm. These involve including unit and multi-delay timing models, a logic model with unknown value, new gates, new types of functions, as well as bit-parallel simulation. Further, it is being redesigned so as to reduce both the complexity of the simulation and the number of events processed during simulation. Additional activities include extending the existing model to a multiple processor implementation, and to handle asynchronous sequential circuits. Application of the Inversion Algorithm to hierarchical simulation and incremental compilation is being explored.