Timing Issues in the Design of Digital Systems

这项研究是关于设计整个数字系统(例如微处理器)的时序验证和优化框架。这项研究建立在一个广泛使用的同步时序分析模型和一种估计门和线延迟的有效方法的基础上。该模型正在扩展，以包括相关的功能信息，以提高准确性。该框架的组件包括：分离关键元件的设计分解；路径延迟计算器；寻找同步器组件的算法；时钟分析算法；符号顺序时序验证组件；混合时序逻辑模拟器；以及设计优化器。

This research is on a timing verification and optimization framework for designing an entire digital system (e.g. a microprocessor). The research builds on a widely used model for synchronous timing analysis and an efficient method for estimating gate and wire delays. The model is being extended to include relevant functional information in order to enhance accuracy. Components of the framework are: design decomposition to isolate critical elements; a path delay calculator; algorithms for finding synchronizer components; clock analysis algorithms; a symbolic sequential timing verification component; a hybrid timing-logic simulator; and design optimizers.