Exploring the Design Space for High Performance and Low Cost Memory Hierarchies

本研究的主要目的是探讨一些创新的高速缓存设计技术的硬件设计和性能评估相关的问题。 这些设计技术目前正在开发的单芯片通用处理器和多处理器。 具体而言，研究的重点包括：1）通过CAT--缓存地址标签，最小化片上缓存的面积开销; 2）通过在程序执行过程中频繁变化的少量标签位，将数据均匀地分布在多个缓存集上，最大化缓存命中率; 3）研究新的CAT高速缓存设计对各种高速缓存配置以及多处理器高速缓存的潜在影响;以及4）设计分析模型，并执行跟踪驱动的仿真和执行驱动的仿真，以评估各种设计的实现成本、性能和设计权衡。

The main objective of this research is to investigate the issures related to hardware designs and performance evaluations of a number of innovative cache design techniques. These design techniques are currently being developed for single-chip general purpose processors and multiprocessors. Specifically, the focus of the research includes: 1) minimization of area cost of on-chip caches by CAT--caching address tags: 2) maximization of cache hit ratios by evenly distributing data across cache sets with the help of a few tag bits that change frequently during program executions; 3) investigation of potential impacts of the new CAT cache designs for various cache configurations as well as multiprocessor caches; and 4) devising analytical models, and performing trace-driven simulations and execution-driven simulations for evaluating implementation costs, performances, and design trade-offs of various designs.