VLSI Delay Vernier Architectures and Applications

本项目关注从波管道发展而来的超大规模集成电路系统的两种性能增强技术：延迟游标架构和非零偏差设计方法。许多高性能应用程序需要非常精细的定时分辨率或非常高的数据采样率。示例包括高速网络收发器，A/D转换器，锁相和锁延迟和锁延迟环路，以及ATE引脚电子器件。通常，昂贵的电路技术和非常高频的时钟信号被用来满足这些性能要求。然而，所提出的延迟游标结构能够使用CMOS技术和相对较慢的时钟信号实现非常高的时间分辨率。本研究将集中于改进和扩展延迟游标架构和设计技术，使其效用最大化。将评估该体系结构在许多应用程序中的有效性。此外，一些现实世界的因素，如工艺变化和噪声，将被调查。非零倾斜设计方法允许VLSI系统设计人员利用有意倾斜来优化特定传播延迟集的时钟分布，从而大大提高系统吞吐量。对于这些系统来说，产生精确时钟偏差的能力是至关重要的。这项研究将非常强烈地关注延迟游标技术，因为它可以提供这种所需的能力。最后，将为几个有前景的应用构建原型系统。

This project is concerned with two performance enhancing techniques of VLSI systems that have developed from wave pipelining: delay vernier architectures and non-zero skew design methodologies. Many high performance applications require extremely fine timing resolution or very high data sampling rates. Examples include high speed network transceivers, A/D converters, phase-locked and delay- locked and delay-locked loops, and ATE pin electronics. Normally, expensive circuit technologies and very high frequency clock signals are used to satisfy these performance requirements. However, the proposed delay vernier structures are capable of achieving a very high time resolution using CMOS technologies and relatively slow clock signals. This research will focus on refining and extending delay vernier architectures and design techniques so that their usefulness is maximized. The effectiveness of the architecture in a number of applications will be evaluated. Also, some real-world factors, such as process variation and noise, will be investigated. The non-zero skew design approach allows the VLSI systems designer to take advantage of intentional skew to optimize clock distribution for a particular set of propagation delays, and thereby greatly improve system throughput. A critical necessity for these systems in the ability to create precise clock skews. This research will focus very strongly on the delay vernier technique, since it can provide this required ability. Finally, prototypes systems will be built for several promising applications.