Research in High-Frequency Analog Electronic Circuits for Communication Systems

本研究涉及电子电路设计的新方法的创建，这将允许实现更小的尺寸，更长的电池寿命和更低的成本在个人通信系统，如蜂窝电话，无绳电话和无线计算机网络。此外，正在研究新的收发器结构，这将允许对用户透明的多标准操作。因此，单个个人通信手机可以在世界任何地方使用，因为它自动调整到不同的本地标准和频率。便携式收发器的当前实现方式通常使用具有多个精密外部滤波器、谐振器和其他组件的多芯片、多技术方法，以便满足此类系统中的模拟RF接口的严格性能要求。这些过渡方法严重限制了可实现的功率耗散和形状因子水平，并且与低成本自适应多标准操作不兼容。这项研究正在探索新的架构和电路技术，这将允许利用规模化的CMOS超大规模集成电路技术集成整个收发器功能，只有少数外部元件。挑战在于找到新的方法，通过利用缩放的集成MOS晶体管固有的高带宽能力，克服集成无源元件的固有限制，例如集成电感器、电容器和变容二极管中的低Q值。研究人员希望在本研究项目结束时演示一个单芯片多标准RF收发器，该收发器包含合成器、发送路径、功率放大器和接收路径，并提供与几种不同RF标准的接口。该原型将在0.35微米CMOS工艺中实现。

This research is concerned with the creation of new methods of electronic circuit design which will allow realization of smaller size, longer battery life and lower cost in personal communication systems such as cellular telephones, cordless telephones and wireless computer networks. In addition, new transceiver architectures are being investigated which will allow multistandard operation which is transparent to the user. Thus, a single personal communication handset could be used anywhere in the world as it automatically adjusts to different local standards and frequencies. Current implementations of portable transceivers typically use a multi-chip, multi-technology approach with a number of precision external filters, resonators, and other components in order to meet the stringent performance requirement of the analog RF interface in such systems. These transitional approaches severely limit the achievable levels of power dissipation and form factor, and are not compatible with low- cost adaptive multistandard operation. This research is exploring new architectures and circuit techniques which will allow utilization of scaled CMOS VLSI technology to integrate the entire transceiver function with only a few external components. The challenge is to find new approaches that overcome the inherent limitations of integrated passive components such as low Q values in integrated inductors, capacitors and varactors, by utilization of the inherently high bandwidth capabilities of scaled integrated MOS transistors. The investigators expect to demonstrate at the end of this research project a single-chip multistandard RF transceiver incorporating synthesizers, transmit path, power amplifier, and receive path as well as providing interface to several different RF standards. This prototype will be implemented in 0.35 micron CMOS technology.