CISE Experimental Partnerships: An Experimental Configurable Computing System for Wireless Communications

99-01377华盛顿大学Ebeling，CarlHuu，刘大学实验合作伙伴：用于无线通信的实验可配置计算系统基于快速体系结构的实验可配置计算系统正在构建中，该系统将展示粗粒度可配置计算体系结构在信号和图像处理领域的优势。利用该实验系统构建、演示和分析了智能天线CDMA无线基站原型系统，重点研究了基于Xilinx Virtex大规模可编程门阵列的快速可配置架构的仿真。该快速仿真系统具有与单芯片快速系统相同的功能，而单芯片快速系统是该体系结构的最终目标。我们的目标是使仿真有足够的性能以50 MHz的目标速度运行，以演示实时应用程序，如码分多址无线基站。使用现场可编程门阵列对快速体系结构的每个组件进行仿真，包括数据路径、数据路径控制器、流控制器和存储器控制器。这个实验系统被用来模拟最终的快速体系结构。也就是说，为了提供对快速体系结构的成本和性能的准确测量，以一种受快速体系结构约束的方式操作现场可编程门阵列。该仿真系统提供了探索与RAPID相关的许多替代体系结构和系统想法的机会。这种探索可能导致将快速体系结构有效地定义为片上系统技术中的计算核心。

99-01377Ebeling, CarlHui, LiuUniversity of WashingtonCISE Experimental Partnerships: An Experimental Configurable ComputingSystem for Wireless CommunicationAn experimental configurable computing system based on the RaPiD architecture is being constructed that will demonstrate the advantages of coarse-grained configurable computing architectures in the domain of signal and image processing. The work involves the construction, demonstration and analysis of a prototype smart antenna CDMA wireless basestation using this experimental system.The focus of this research is the emulation of the RaPiD configurable architecture using the large Xilinx Virtex FPGAs that have recently become available. This RaPiD Emulation System has the same functionality as a single-chip RaPiD system that is the eventual target of this architecture. The goal is for the emulation to have sufficient performance running at a target speed of 50 MHz to demonstrate real-time applications such as the CDMA wireless basestation. Each component of the RaPiD architecture is emulated using FPGAs, including the datapath, the datapath controller, the stream controllers and the memory controller. This experimental system is being used to emulate the final RaPiD architecture. That is, the FPGAs are operated in a way that is constrained by the RaPiD architecture in order to provide an accurate measure of the cost and performance of the RaPiD architecture. This emulation system provides opportunities to explore many alternative architectural and system ideas related to RaPiD. This exploration could lead to an efficient definition of the RaPiD architecture as a computational core in system-on-a-chip technology.