U.S.-Japan Cooperative Science: Synthesis and Verification of High Performance Timed Circuits and Systems

0087281Myers该奖项支持犹他州大学的Chris Myers教授和日本东京工业大学的Tomohiro Yonder教授之间为期三年的合作研究项目。研究人员将对高性能定时电路和系统的综合和验证进行研究。为了继续生产速度越来越快的电路，设计者正在考虑积极的电路设计风格，如自重置或延迟重置多米诺电路。这些设计风格可以实现电路速度的显著提高，正如它们在IBM的千兆赫兹研究微处理器D(Guts)中的使用所证明的那样。由于潜在的更高的性能和更低的功耗，设计人员也在考虑异步电路，英特尔设计的RAPPID指令长度解码器就证明了这一点。这种设计的速度是同步设计的三倍，而只使用同步设计的一半功率。然而，使用传统的静态时序分析方法不能有效和准确地分析这些新的时序电路类型。缺乏分析工具是这些设计风格不被主流接受的原因之一。合作者的目标是开发实用工具，用于合成和验证定时电路设计风格。他们将计划统一两组研究人员的分析和验证方法的最佳方面，然后计划开发工业规模系统的综合和验证技术。这些系统将包括数据路径和控制电路的组合。他们将开发使用自动抽象的方法，其中数据路径组件将被部分验证，并完全控制部分。然后，他们将使用分层信息来确定如何执行抽象。该项目汇集了两个拥有互补专业知识和研究能力的实验室的努力。这项研究通过研究生的参与促进了国际人力资源的发展。通过思想和技术的交流，这个项目将扩大我们的基础知识基础，促进国际理解与合作。研究人员计划在科学期刊上发表研究结果，并在科学会议上报告研究结果。

0087281MyersThis award supports a three-year collaborative research project between Professor Chris Myers of the University of Utah and Professor Tomohiro Yonder of the Tokyo Institute of Technology in Japan. The researchers will be undertaking a study of synthesis and verification of high performance timed circuits and systems. In order to continue to produce circuits of increasing speeds, designers are considering aggressive circuit design styles such as self-resetting or delayed-reset domino circuits. These design styles can achieve a significant improvement in circuit speed as demonstrated by their use in a gigahertz research microprocessor d(guTS) at IBM. Designers are also considering asynchronous circuits due to potential higher performance and lower power as demonstrated by the RAPPID instruction length decoder designed at Intel. This design was three times faster while using only half the power of the synchronous design. These new timed circuit styles, however, cannot be efficently and accurately analyzed using traditional static timing analysis methods. This lack of analysis tools is one of the reasons for the lack of mainstream acceptance of these design styles. The collaborators aim to develop practical tools for the synthesis and verification of timed circuit design styles. They will plan to unify the best aspects, from both groups of researchers, of their analysis and verification methodologies and then plan to develop techniques for the synthesis and verification of industrial-scale systems. These systems will include a combination of both datapath and control circuits. They will develop methods using automated abstraction in which datapath components will be verified partially and control parts completely. They will then use hierarchical information to determine how the abstraction is to be performed.The project brings together the efforts of two laboratories that have complementary expertise and research capabilities. This research advances international human resources through the participation of a graduate student. Through the exchange of ideas and technology, this project will broaden our base of basic knowledge and promote international understanding and cooperation. The researchers plan to publish results of the research in scientific journals and report on the findings at scientific meetings.