CAREER: Analog VLSI Integrated Circuits for Real-Time Neural Control

这个项目将开发一种新的芯片类别，能够在芯片本身上进行高吞吐量学习，实现神经网络学习的新概念，这应该允许芯片学习如何以非常通用的方式控制制造工厂或车辆，适用于广泛类别的任务。作为试验台，该项目将开发神经网络学习算法和芯片，以提高由PI的合作者在佐治亚理工学院开发的先进半导体制造设计的性能。如果成功，这项工作可能会大大加快学习系统在工程应用中的使用。对于非常广泛的信息处理任务，它最终可以使每个芯片的有效计算吞吐量大幅提高，超过摩尔定律(芯片的物理特征密度和速度的增加)可能带来的改进。这个项目建立在PI开发模拟可计算存储器或模拟计算阵列的先前工作的基础上，其中他使用存储元件本身来执行计算，而不是存储外部处理器使用的模拟值。这些系统基于密集浮栅晶体管阵列，提供非易失性存储，计算存储的重量和输入之间的乘积，允许编程而不影响计算，并根据流经芯片的信息随时间进行调整。原则上，这项技术允许开发具有与专用模拟ASIC芯片相当的吞吐量的通用芯片，但由于底层架构的权重和通用逼近能力的适应，具有一种通用的灵活性。

0093915HaslerThis project will develop a new class of chips capable of high-thruput learning on the chip itself, implementing new concepts of neural network learning which should allow the chips to learn how to control manufacturing plants or vehicles in a very generalized way, applicable to a wide class of tasks. As a testbed, the project will develop neural network learning algorithms and chips to improve the performance of advanced semiconductor fabrication designs being developed by the PI's collaborators at Georgia Tech. If successful, this work could significantly accelerate the use of learning systems for engineering applications in general. It could eventually allow a substantial improvement in effective computational throughput per chip, above and beyond the improvements possible through Moore's Law (the increase in the physical feature density and speed of chips), for a very broad range of information processing tasks.This project builds on the PI's prior work developing analog computable memories, or analog computing arrays, where instead of storing the analog values to be used by external processors, he uses the memoryelement itself to perform the computation. These systems are based on arrays of dense floating-gate transistors that provide nonvolatile storage, compute a product between stored weights and inputs, allow for programming that does not affect the computation, and adapt over time based on the information flowing through the chip. In principle, this technology permits the development of general purpose chips with throughput comparable to that of dedicated analog ASIC chips, but with a kind of universal flexibility due to the adaptation of the weights and the universal approximation capabilities of the underlying architectures.